Sr. SI/PI Engineer - Serdes, Satellites (Starlink)

SR. SI/PI ENGINEER - SERDES, SATELLITES (STARLINK)

SpaceX is leveraging its experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact. As we continue to upgrade and expand the constellation, we’re looking for best-in-class engineers to join the team.

As a Signal and Power Integrity Engineer on Starlink’s Payload Engineering team, you’ll have SI and PI ownership throughout the entire life-cycle of the portfolio of hardware that enables this connectivity, and sits at the intersection of electrical, mechanical, thermal analysis, software, and antenna/RF engineering. Early in any given product’s design cycle, your work will include everything from IP evaluation in the silicon architecture stage, package performance evaluation, stackup material selection and characterization, channel and PDN architecture, and PCB layout oversight. Once hardware is in hand, you will drive troubleshooting, characterization, qualification, and general debug across all phases of the product’s life.

As a subject matter expert on SI and PI, you will define the design, analysis, and verification processes and tools that the Starlink team uses when developing hardware. You will have wide latitude to determine how best to tackle these problems and be expected to spread the associated knowledge and techniques to engineers across the Starlink program.

RESPONSIBILITIES:

• Specify, design, simulate, verify, qualify, define production screens for, and generally troubleshoot SI and PI aspects of advanced satellite hardware, such as:
  
  
  
  • Wireline and electro-optical communication systems with cutting edge (e.g. 10 to 112+ Gbps) SERDES, DSPs, retimers, and optoelectronics
  
  
  • High-speed and high-bandwidth memory interfaces (DDR4, LPDDR5, GPDDR6, QSPI NOR, eMMC, etc.)
  
  
  • Power needs and PDNs for the associated ASICs
  
  


• Work alongside RF engineers, antenna engineers, ASIC engineers, packaging engineers, mechanical engineers, thermal engineers, software engineers, supply chain, and production engineers (among others) to architect new products which will employ novel channels, interfaces, and power delivery strategies


• Derive top level specifications for PCB materials and channel subcomponents


• Design and optimize transition structures for the entire channel from die bump to die bump


• Drive detailed component selection to accompany your PDN designs


• Root cause and fix issues found in PCB manufacturing, PCBA test, or satellite integration


• Define best practices, simulation workflows, test methodologies, signoff criteria, and lab equipment needs for all SI/PI needs on Starlink satellite payloads

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or physics


• 5+ years of industry experience designing circuits, electronic products, or hardware


• 2+ years of experience using one of the 3D EM simulation tools and high-speed digital channel simulators (CST, HFSS, ADS etc.)


• 2+ years of research or industry experience with high-speed digital design or power integrity

PREFERRED SKILLS AND EXPERIENCE:

• Master’s degree or PhD in electrical engineering, computer engineering with emphasis in electromagnetic theory, transmission line theory, wireline transceivers, or power integrity


• 5+ years of electronic product experience designing hardware from concept through production; strong emphasis on full life-cycle development of new hardware products and not small incremental updates to legacy hardware


• 5+ years of experience architecting, implementing, and debugging cutting edge DSP based SERDES products (i.e. 56Gbps, 112Gbps, 224Gbps) working across package and PCB


• 5+ years of experience specifying, analyzing, debugging, and working with high speed, high bandwidth memory interfaces


• 5+ years of experience designing, implementing, and debugging power delivery networks for large processors, FPGAs, SoC, or ASICs with complex power requirements


• Thorough understanding of wireline transceiver concepts, architectures, and circuits


• Strong understanding of computers and programming languages (Python, C/C++)


• Demonstrated ability to work in a highly cross-functional role


• Experience with low loss laminates, high volume PCB manufacturing, and high-speed connectors


• Experience debugging and resolving EMI/EMC de-sense problems


• Passion for working in dynamic cross-functional role to optimize package, PCB, ASIC, mixed signal circuit to deliver best in class products

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours or weekends as needed for mission critical deadlines


• Some travel may occasionally be required

COMPENSATION AND BENEFITS:

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k)-retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.